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To Conquer SoC Design Challenges, Change EDA Methods and Tools

— is performed separately by an ultra- application. The power architecture or intent
specialized team of engineers, and achieving is captured in a Unified Power Format (UPF)
the completed design requires close commu- database. Before assembling or promoting
nications and continual information exchange power information at the SoC level (Figure 2a),
among the disparate teams. Each new iteration power information for the different blocks is
of a design restarts the information exchange extracted. Traditionally, power extraction has
process. As a result, the higher the number of been a tedious, manual process. UPF demotion
iterations, the greater the impact on the proj- (Figure 2b), however, is increasingly a process
ect’s final cost and time to completion. that requires full automation.
One reason that the traditional SoC
integration flow inevitably generates many FACILITATE DESIGN-SPACE EXPLORATION
iterations is register-transfer–level (RTL) Another shortcoming of traditional SoC inte-
design, which needs to be fine-tuned and gration approaches is insufficient automation
incrementally optimized until the RTL2GDS of the process for exploring the design space
synthesis process reaches the best PPA result. and determining the best PPA design configu-
Also, design reuse of soft IP cores from previ- ration. The amount of engineering resources
ous projects needs to increase to much higher required to run multiple what-if scenarios
ratios in order to extract more value from manually may be excessive, preventing design
designs and to make IP cores and SoCs off- teams from achieving optimized solutions.
the-shelf commodities. Finally, cutting-edge Equipped with the physical design infor-
change in design methodologies — represent- mation, EDA tools should enable physically
ing a radical departure from traditional EDA aware SoC assembly by creating different
practices and tools — must occur to accom- design configurations at the register-transfer
plish the higher number of tasks that today’s level. This allows RTL detection and cor-
SoC projects require without stretching rection of problems that designers would
engineering resources too thin. It is worth otherwise discover only after synthesis. Such
noting that most of the EDA innovations are issues include connectivity problems, which
expected to happen at the architectural level, can make placement and routing (P&R) a
during the SoC integration and before RTL- painful process.
2GDS implementation.
The methodology changes described below MAKE EDA TOOLS SMARTER
will help overcome the challenges. Applications are expanding for AI and its
derivatives, particularly machine learning
START THE SoC BUILD PROCESS MUCH (ML). The EDA community cannot neglect the
EARLIER opportunity to leverage ML algorithms when
Accelerating this process requires that EDA working to resolve SoC design challenges.
design tools provide a much higher degree of From system-level to physical design, each
automation when handling design informa- EDA tool is usually built on top of complex
tion. The solution is a unified database that algorithms, regardless of the design task
accommodates a variety of design domains (simulation, formal verification, synthesis,
and formats. All design information, including DFT, P&R, etc.). The key challenge is to make
RTL, timing constraints, power, physical, and such algorithms AI-/ML-compliant and let
test, must be taken into consideration as early them benefit from the tremendous amount of
as possible in the SoC build process. collected data at their disposal when running
Such an approach, in practice, should on a large volume of design projects.
allow non-domain experts to make import- Let’s take a simple case of SoC top-level
ant design decisions. For example, a CAD integration. A typical outcome from
engineer or RTL designer would have the AI/ML might be an optimal selection of SoC
capability to build a first SoC configuration configurations to reach aggressive PPA, such
from design assembly to synthesis. as a much smaller area or a drastic decrease
in CPU time. Without real production data,
MAXIMIZE DESIGN REUSE however, AI/ML is useless. Therefore, tight
Substantial resources are expended when collaboration between EDA tool providers and
building configurable IP subsystems for end users is a key success factor.
complex SoCs. Lowering the overall cost of In summary, given the pace of AI/ML
SoC design therefore requires a much higher adoption in other industries, such as robotics
IP-reuse ratio than has traditionally been the and health care, EDA tool providers’ AI/ML
case, and meeting that challenge requires a initiatives appear timid by comparison. But
new class of design reuse methodologies and the industry cannot afford to ignore AI/ML
tools. During the SoC integration process, EDA outcomes for EDA. ■
tools must provide generic APIs with basic and
advanced design extraction capabilities. Chouki Aktouf is CEO of chip design
Let’s consider the example of an SoC software provider Defacto Technologies
integration requirement for a low-power (Grenoble, France).

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