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To Conquer SoC Design Challenges, Change EDA Methods and Tools

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To Conquer SoC Design Challenges,

Change EDA Methods and Tools

By Chouki Aktouf

ystems-on-chip are everywhere,
especially in electronics serving
emerging market segments such as
S5G, autonomous vehicles, and artificial
intelligence. These complex activities require
real-time processing at billions of operations
per second. As system complexity continues
to rise, SoC design groups are under mounting
pressure to deliver more efficient products at
lower costs and with shorter times to deliver-
ables than ever before — and they’re finding
that traditional design methodologies and
tools are reaching their limits. Breakthroughs
are needed if EDA is to keep ahead of evolving
SoC design challenges.

With SoC design groups
under pressure to deliver
more efficient products at

lower costs, breakthroughs
are needed if EDA is to keep
ahead of evolving SoC design
challenges.

SoC design starts with the integration
process, in which the selected
intellectual-property blocks must be inter-
connected. The challenge is reaching the best
possible power, performance, and area (PPA)
combination within tight deadlines while
keeping engineering costs under control. In the
traditional EDA design flow, each task — power
consumption, architecture, testing, and so on Figure 1: Unified handling of design information

Figure 2: Power design reuse during SoC integration. Top-level power integration (a) proceeds from power design extraction (b).

FEBRUARY 2021 | www.eetimes.eu