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58 EE|Times EUROPE
Five Keys to Next-Generation IC Packaging Design

of signoff errors and prevent signoff bottle- while collaborating across geographies and
necks and delays. departments, using rapid prototyping and
One hallmark of IC verification has been co-design to evaluate substrate routability,
the use of multiple, specialized EDA tools electrical and thermal performance, and
within a single framework to enable designers testing. As methodologies and flows mature,
to perform a wide variety of verification pro- system-level designers also need to know For reader inquiries and address changes,
cesses. The goal is the same when automating whether package DRC, LVL verification, and please contact: christiane.lockner@aspencore.com
or call +49 8092-247740
heterogeneous package assembly verification. assembly-level LVS are sufficient to guarantee To unsubscribe, please go to:
Heterogeneous verification is significantly correct functionality and successful manufac- www.eetimes.eu/unsubscribe/
simplified based on the premise that each turing of the heterogeneous assembly.
individual die has already been checked With a single environment for manag-
against its target foundry rules. It’s also critical ing all of these processes in an efficient, Aspencore Media GmbH
to maintain independence between the design repeatable, and automated flow, designers Frankfurter Straße 211
63263 Neu-Isenburg
and verification environments to ensure the can better anticipate and eliminate potential Germany
veracity of verification results. downstream issues, efficiently perform and EDITORIAL MANAGEMENT
Verification includes DRC to verify the evaluate tradeoffs and design scenarios, Junko Yoshida, Global Editor-in-Chief,
interactions between die components and and clearly communicate decisions junko.yoshida@aspencore.com
may require extracting several layers within to stakeholders. Jürgen Hübner, Managing Editor, j.hubner@aspencore.com
Anne-Françoise Pelé, Editor-in-Chief, EE Times Europe,
each die to see these interactions. Physical Finally, known-good–die testing and afpele@aspencore.com
verification also includes LVL checks for package-level test generation are critical Brian Santo, Editor-in-Chief, EE Times,
brian.santo@aspencore.com
alignment between substrates, scaling or prior to stacking in 2D and 3D heterogeneous Echo Zhao, Chief Analyst, echo.zhao@aspencore.com
compensation factors, and pad centers or assemblies. Test teams should reuse die-level, Judith Cheng, Managing Editor,
overlaps. For an EDA tool, engineers must built-in self-test, and scan patterns by map- Judith.cheng@aspencore.com
understand how to differentiate the layering ping them up to the package level. Boundary CONTRIBUTING EDITORS
George Leopold, gleopold@gmail.com
per die and per placement. Moreover, the tool scan testing of the package interconnect Ann Thryft, athryft@earthlink.net
should leverage the digital-twin virtual mod- structures ensures that the I/Os are actually STAFF CORRESPONDENTS
el’s data to automatically extract the correct connected and can identify any substrate Matthew Burgess, matthew.burgess@aspencore.com
assembly representation in order to perform fabrication or assembly issues. Anthea Chuang, anthea.chuang@aspencore.com
Nitin Dahad, nitin.dahad@aspencore.com
the DRC and LVL checks. Maurizio Di Paolo Emilio,
Connectivity checking — LVS — in an COMPLETE DESIGN AND VERIFICATION maurizio.dipaolo@aspencore.com
Yvonne Geng, yvonne.geng@aspencore.com
IC looks at the connected shapes and pin FLOW Amy Guan, amy.guan@aspencore.com
locations derived from physical layout data For many applications, next-generation IC Susan Hong, susan.hong@aspencore.com
to produce the physical netlist, which is com- packaging is the best path to achieve silicon Illumi Huang, illumi.huang@aspencore.com
Barbara Jorgensen, barb.jorgensen@aspencore.com
pared against the golden schematic netlist to scaling, functional density, and heteroge- Majeed Ahmad Kamran, majeed.kamran@aspencore.com
verify connectivity. Connectivity checking is neous integration while reducing the overall Clover Lee, clover.lee@aspencore.com
Shao Lefeng, lefeng.shao@aspencore.com
performed at each substrate level and across package size. Integrating multiple devices Jenny Liao, jenny.liao@aspencore.com
substrates. An automated, package LVS flow in into a single package supports system scaling Elaine Lin, elaine.lin@aspencore.com
Luffy Liu, luffy.liu@aspencore.com
its simplest form must ensure that the inter- demands, reduces system real estate, lowers Challey Peng, challey.peng@aspencore.com
poser and package GDSII correctly connect die manufacturing costs, and often increases Gina Roos, gina.roos@aspencore.com
to die (for multi-die systems) and die to quality and reliability. Fendy Wang, fendy.wang@aspencore.com
Sally Ward-Foxton, sally.wardfoxton@aspencore.com
C4/BGA bumps (for both single-die and multi- Next-generation IC packaging designs need Demi Xia, demi.xia@aspencore.com
die systems) as intended by the designer. a new approach for design and verification at Franklin Zhao, franklin.zhao@aspencore.com
Momo Zhong, momo.zhong@aspencore.com
The system netlist is compiled from the all levels, starting with the use of a COPY AND DESIGN
digital twin of the overall assembly, as dis- digital-twin virtual prototype model that Adeline Cannone, Design Director,
cussed earlier. This system or golden netlist drives all aspects of design and verifica- adeline@cannone.com
is then compared against the physical design tion, even if different design tools are used, Lori O’Toole, Chief Copy Editor, lotoole@aspencore.com
Diana Scheben, Senior Copy Editor,
connectivity derived from the manufacturing enabling designers to manage all of these diana.scheben@aspencore.com
data. The virtual model can highlight warn- processes in an efficient, repeatable, and TECHNICAL AND ADMINISTRATIVE SERVICES
ings or violations, so designers can trace and automated flow. Tracey Bayer, tracey.bayer@aspencore.com
debug errors with the help of an EDA tool. Mentor, a Siemens Business, offers a SALES & MARKETING
The 2.5D and 3D heterogeneous packages high-density advanced packaging solution Christiane Lockner, christiane.lockner@aspencore.com
typically incorporate multiple devices and developed specifically to address the five The Hufmann Agency, victoria@hufmann.info,
norbert@hufmann.info
multiple substrates to deliver the required keys to next-generation IC packaging design. Todd Bria, todd.bria@aspencore.com
solution for system scaling and performance. This complete design and verification flow Martin Chatterton, Group Publisher, ASPENCORE
With decreasing delineation between die and integrates the industry’s gold standard in veri- Copyright© All rights reserved. No part of this publication
substrate, the proximity of these elements fication. Calibre 3DStack, along with Xpedition may be reproduced or transmitted in any form or by any
greatly enhances chip-package interactions, Substrate Integrator and Xpedition Package means without the prior express written permission of
Aspencore Media. Although we make every effort to present
necessitating a unified co-design flow. With Designer, leverages HyperLynx and FloTherm up-to-date, accurate information, EE Times Europe will not
critical elements like high-speed interfaces for cross-domain multi-physics analysis. ■ be responsible for any errors or omissions or for any results
obtained from the use of such information. The magazine
or power delivery, a decision on one substrate will not be li able for any loss caused by the reliance on
can have a ripple effect on adjacent substrates Keith Felton is marketing manager for information obtained on this site. Furthermore, EE Times
or impact the entire system. Xpedition IC Packaging Solutions at Mentor Europe does not warrant the accuracy or completeness
of the information, text, graphics in this magazine. The
Designers must find ways to manage Graphics. This article was originally published opinions expressed in the articles are those of the authors
multiple substrates in a single environment on EDN. and not necessarily the opinions of the publisher.

FEBRUARY 2021 | www.eetimes.eu