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Five Keys to Next-Generation IC Packaging Design

The 2.5D and 3D heterogeneous designs typically use through- the same design across local or global networks, yet retain the ability
silicon vias (TSVs), which are long vias extending through the die or sub- to visualize all design activity without having to endure any onerous
strate to connect the front and back sides. TSVs allow dies and substrates setup or process management.
to be stacked and directly interconnected. However, in addition to their
own significant electrical characteristics, TSVs have an indirect effect on PRECISION MANUFACTURING HANDOFF
the electrical behavior of devices and interconnects in their vicinity. Another common challenge is the time required for verification signoff
To model a 2.5D/3D heterogeneous system accurately, a designer prior to manufacture. The proven way to avoid this bottleneck and
needs tools that extract precise electrical parameters from the physical its related impacts is to implement a process and methodology of
structure of the 2.5D/3D elements. Those parameters can then be integrated and continuous verification so that the final verification
fed into behavioral simulators. Utilizing the 3D digital-twin model of signoff process is controlled and manageable. This means providing
the complete package assembly, designers can accurately extract the manufacturing-error–free fabrication and assembly data that passes
parasitics of the 2.5D and 3D models. Once the elements have been the foundry’s or OSAT’s process rules (PDK or PADK). The goal and the
extracted correctly, using the appropriate methodology and process, challenge are to achieve this in the first pass.
they can be assembled into a system-level interconnect model and sim- Eliminating iterations requires a design environment with the
ulated to analyze performance and appropriate protocol compliance. capabilities and features to meet process rules without relying on
hit-or-miss manual methods that will likely require multiple design
spins to achieve the handoff criteria. In order to avoid multiple design
revisions to pass the manufacturer’s rules, automation is mandatory.
Advanced IC packaging is almost always fabricated using GDSII. It
is this GDSII file that the fabricator, foundry, or OSAT will verify for
compliance to their manufacturing rules and constraints, which, of
course, leads to a common dilemma: The GDSII file is post-processed
from the design tool’s native CAD database, and that’s where problems
can and do occur.
No matter how well your CAD design tool can produce geometries
that meet the manufacturer’s fabrication rules, it’s the post-process–
derived GDSII that will be used for signoff, and that’s the Achilles’ heel
of most IC package CAD design tools today. The actual design in CAD
may pass as compliant, but because of poor-quality geometry post-
processing, the resultant GDSII rarely does. That’s what typically leads
to design spins as the designer struggles to achieve acceptable GDSII.

GOLDEN SIGNOFF
The precise creation of a manufacturing-defined structure is For advanced IC packages, golden signoff requires a comprehensive set
critical if re-spins are to be avoided. (Source: Mentor Graphics) of checks, or else total assembled device yield will not hit targets and
will overrun projected assembly and test costs. Comprehensive golden
SCALABILITY AND RANGE signoff should include, at a minimum, physical verification, connectiv-
Heterogeneous packaging technologies are more complex to design, ity checking (aka LVS), and heterogeneous assembly-level verification
fabricate, and assemble, potentially limiting their availability to all but (aka LVL). Such a comprehensive signoff checking process can highlight
the leading semiconductor companies and their bleeding-edge designs. many issues that require rework. If not detected, those issues can easily
Fortunately, the design and supply chain ecosystem can play a powerful delay projects, add costs, and lead to missed manufacturing schedules.
role in enabling the democratization of such technologies, putting One way to prevent this from happening is to implement a shift-
them within the reach of all designers and companies — just as the left design flow, performed in-design to locate and eliminate obvious
silicon foundry world did with process design kits (PDKs), which have signoff errors. Using such a methodology can remove more than 80%
become ubiquitous.
Automated IC verification is driven by design rules created by the
foundry and provided in a PDK to design houses. EDA tool suppliers
qualify their toolsets against these rules to ensure their verification
tools produce proven, repeatable, signoff-quality results. The purpose
of a package assembly design kit (PADK) is similar to that of the PDK:
to facilitate manufacturability and performance using standardized
rules that ensure consistency across a process.
Obviously, a PADK must include both a physical verification and
extraction signoff solution, and it should also address thermal and/or
stress signoff solutions. All of these processes should be independent of
any specific design tool or process used to create the assembly. In addi-
tion, a complete PADK must work across both IC and packaging domains,
implying that the flow must support multiple formats. Finally, all of
these verification processes must be validated by the package assembly/
outsourced semiconductor assembly and test (OSAT) company.
The scale and complexity of advanced IC packages put immediate
pressure on the designer and the design schedule, which often gets
extended. An emerging popular approach to managing this is concur- Integrated geometry-based DRC can prevent excessive signoff
rent team design, wherein multiple designers simultaneously work on errors. (Source: Mentor Graphics)

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