Page 51 - PEN Ebook March 2021

SEMICONDUCTORS Semiconductors

POWER GAN TECHNOLOGY CCPAK: A NEW POWER PACKAGE

GaN technology and specifically GaN-on-Sili- WITH PROVEN HERITAGE
con (GaN-on-Si) High Electron Mobility Transis- Naturally, the GaN technology and operation mode
tor (HEMT) technology has become a key focus are key, but as with any FET device packaging plays
for power engineers over the last few years. Its a critical role. As the market is moving to ever
promise to provide the high-power performance higher switching frequencies, the limitations of tra-
and high frequency switching that many applica- ditional packages (TO-220 / TO-247 and D2PAK-7)
tions are demanding is clear. become increasingly clear. To really take advantage
of the benefits of new high-voltage WBG semicon-
After the introduction of cascode mode technol- ductors, copper clip technology would optimize

ogy in the leaded TO-247 package, a lot of trends both electrical and thermal performance.
have addressed the market towards improve-
ments in terms of R DS(on) , better switching Figure
Of Merit (FOM), lower capacitances.

When it comes to device stability and ease of
operation, the cascode configuration provides

the robust and reliable insulated (dielectric) gate
structure of a silicon gate. That means the cas-
code GaN FET has an effective gate rating of ± 20
V (equal to existing silicon superjunction technol-
ogy) and can be driven by standard cost-effective
gate drivers with simple 0-10 or 12 V drive volt-
age, while offering high gate threshold voltage of
Power GaN technology 4V for immunity against false turn on. Figure 2: Internal arrangement of CCPAK1212.

and copper-clip Nexperia proposed CCPAK package to offer the

advantages of copper clip to Power GaN FET
packaging solutions. CCPAK1212 equates to about one fifth
(21.4%) the body size of a TO-247 or alternatively
a 10% more compact footprint than the D2PAK-7

By Dr. Dilder Chowdhury – GaN Device Architect, Power GaN Technology at while allowing lower Rdson product,
Nexperia
By eliminating internal wire-bonds, the CCPAK
offers lower inductances than leaded packag-
Growing pressure from society and increasing limited in operating frequency, speed, and have es. The table in figure 3 highlights the compar-
legislation for reduced CO2 emissions is pushing poor high-temperature performance and low- ison of CCPAK1212 and TO-247 operating at 100
industries from automotive to telecoms to invest current characteristics. High voltage Si FETs are MHz, which results in a total loop inductance
in more efficient power conversion and increased also limited in frequency and high-temperature of 2.37 nH compared to almost 14 nH. But the
electrification. Traditional silicon-based power performance. So, designers are increasingly copper-clip package also helps deliver ultra-low
semiconductor technologies like insulated-gate looking to wide bandgap (WBG) semiconductors package resistance including a thermal resist-
bipolar transistors (IGBTs) are fundamentally in efficient copper-clip packaging. Figure 1: Bidirectional characteristics of GaN FET. ance of < 0.5 K/W.

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