Page 21 - PEN eBook March 2023

DESIGN Design

loss, improved efficiency, simpler converter topologies and significantly improved high-temperature
ratings and performance, as well as reduced size, weight and system costs.

The packaging of these high-voltage (HV, >3.3-kV–rated) SiC devices and modules for use in these
MV grid applications poses several challenges. This article summarizes work done by Professor
Christina DiMarino and her group at the Virginia Tech Center for Power Electronics Systems
(CPES) on high-density, high-speed 10-kV SiC power module packaging. CPES focuses on research
and development dedicated to improving electrical power-processing and -distribution systems,
including power-conversion architectures, power-electronics components, modeling, power quality
and high-density integration.

CHALLENGES IN HV SiC DEVICE/MODULE PACKAGING

▶ Due to their faster switching speeds, SiC devices are more sensitive to parasitic
inductances from the packaging. These can resonate with the device capacitances, causing
undesirable electromagnetic interference. During high-speed current transients (di/dt),
SiC Power Module large overvoltages can be created across the device, which can degrade device reliability

or cause catastrophic fails.
Packaging Solutions for ▶ Parallel devices are often used to achieve module current ratings. Imbalances in parasitic

inductances/capacitances or static device parameters like the threshold voltage can result
MV Grid Applications in varying transient voltage overshoots across the paralleled die. Die with higher overshoots
will see greater switching losses and thus higher temperatures. This can reduce module
lifetimes. External gate resistors are commonly added to control overshoots; however, these
By Sonu Daryanani, contributing writer for Power Electronics News increase switching times and hence losses. Low-inductance wire-bondless interconnect
schemes have been proposed, for example, with metal-post–interconnected parallel
plates. Decoupling capacitors can be used to mitigate the impact of parasitic inductance.
2
Some of the power-electronics applications in medium-voltage (MV) power-distribution and One approach places the capacitors above the power device, creating a vertical power loop
-conversion applications in the range of 1–35 kV include grid-tied inverters and DC/DC converters that keeps the horizontal module footprint unchanged. 3

for renewable energy systems like solar, power management and interruption devices, such as ▶ Traditional power modules include a parasitic capacitance across the insulating ceramic
solid-state circuit breakers, DC/DC converters for DC microgrids and battery-storage systems substrate (such as direct-bonded copper, or DBC) to the heatsink, which is generally at
1
needing bidirectional inverters. ground potential. Under higher-voltage transients (dV/dt), this capacitance becomes a path
for common-mode (CM) current to flow through the system ground. Filters and chokes can
These applications have traditionally relied on silicon (Si)-based devices like insulated-gate bipolar mitigate this; however, they add cost and complexity. A screen layer can be added with the
transistors (IGBTs). Due to their material advantages, including a wider bandgap, lower intrinsic use of multilayer ceramic substrates, which returns the CM current back to the die while
carrier density, higher thermal conductivity and higher saturation velocity, silicon carbide (SiC) also reducing high-frequency noise. 4

power devices offer a number of advantages over Si. These include a lower specific on-resistance ▶ The high electric field created in these HV devices can exceed the breakdown strength
(R ) for a given voltage rating, a higher voltage rating than that available with Si (e.g., up to of dielectric materials in the packaging. This can create partial discharge (PD), which can
DS(on)
15 kV for SiC MOSFETs, versus 6.5 kV for Si IGBTs) and much lower capacitances due to smaller die damage the insulating ceramic substrate. Reducing the electric field, and thereby increasing
sizes for a given R . Combining the benefits of lower conduction and switching losses, higher the PD inception voltage (PDIV), near the insulating substrate is key, as this is typically
DS(on)
switching frequencies and simpler cooling requirements can translate to lower power-conversion where the PD occurs. 5

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