Page 76 - PEN eBook July 2023

Semiconductors

Qorvo’s new TOLL-package devices meet the mentioned requirements due to their:

▶ Reduced package footprint area

▶ Thinner package, allowing thicker heatsinks
▶ Low power losses
▶ Surface-mount–technology package, enabling automated assembly onto PCB daughter
cards for lower cost
▶ Low resistance per package, avoiding the need to parallel multiple FETs
▶ High-current withstand capability and longer short-circuit withstand time
▶ Noise immunity with adequate response time

The advantages of the TOLL’s reduced footprint and height, compared with a conventional D2-PAK

package, are shown in Figure 1.

Figure 1: Size of low-R DS(on) surface-mount offerings—D2PAK7L vs. TOLL (Source: Qorvo)

Gen 4 SiC FETs provide unsurpassed performance across the key figures of merit for R and
DS(on)
output capacitance in the 600-/750-V class of power FETs. Additionally, the devices’ R in the
DS(on)
TOLL packaging, at 5.4 mΩ, is 4× to 10× lower than that of GaN transistors, SiC MOSFETs and best-
in-class silicon MOSFETs. The SiC FETs’ 750-V rating is also 100 to 150 V higher than the competing
technologies, offering a significantly increased design margin for handling voltage transients.

As shown in Figure 1, the TOLL package has a footprint that is 30% smaller and is 50% shorter
in height (2.3 mm) than comparable D2PAK surface-mount alternatives. The TOLL package also
features a Kelvin-source connection for dependable, fast switching of large currents with cleaner
gate waveforms.

76 JULY 2023 | www.powerelectronicsnews.com