Page 26 - PEN eBook February 2024

DESIGN
Optimizing Power
System Loops:
Understanding the
Impact of Gate-Source and
Power Loops
By Saumitra Jagdale, contributing writer for Power Electronics News
A power system is a complicated network of
electrical components that produce, transmit and
distribute power to various loads. The gate-source
loop and the power loop are the two main loops
that make up a power system. The control circuit
that powers the switching device, such as an IGBT
or silicon carbide MOSFET, is called the gate-source
loop. The gate driver, gate resistor, gate capacitance
and gate inductance make up the gate-source loop,
and the device’s performance and switching speed
are set by the gate-source loop.
The primary circuit that transports the load’s voltage
and current is the power loop. This loop is made up
of the power source, the switching device, the load
and parasitic elements like package inductance, PCB
trace inductance and stray inductance. Therefore,
the power system’s dependability and efficiency are
impacted by the power loop.
26 FEBRUARY 2024 | www.powerelectronicsnews.com
The loops in the electricity system are linked and
impact one another. Both the power loop and the
gate-source loop influence how the device switches,
and in the power system loops, parasitic inductances
can lead to several issues, including switching
losses, accidental turn-ons, voltage overshoots and
oscillations in the switching process. To reduce
parasitic inductances and fully utilize SiC devices, it
is crucial to improve the design and architecture of
the power system loops.
SOURCES AND CONSEQUENCES OF
INDUCTIVE EFFECTS
In a power system loop, the inductive effects
are caused by the parasitic inductances of the
components and the layout. Parasitic inductances
are the unwanted inductances that are inherent in
any physical conductor. They are determined by the
geometry, length and proximity of the conductors.
Parasitic inductances can have negative impacts on
Gate-source loops and power loops in a power system circuit (Source: Microchip Technology)
the power system’s performance and reliability. Some
of the common consequences of inductive effects
are:
▶
Voltage overshoot: When the switching device
turns off, the current in the power loop cannot
change instantaneously due to the parasitic
inductance. The parasitic inductance causes
a voltage spike across the device, which can
exceed its breakdown voltage and damage it.
▶ Switching oscillations: The parasitic inductance
and the device capacitance form a resonant
circuit, which can cause ringing at the switch
node. The ringing can increase the switching
losses, electromagnetic interference and noise
sensitivity.
▶ Inadvertent turn-on: The voltage spike and
the ringing can couple to the gate-source loop
through the Miller capacitance and cause a
Voltage overshoot issues during power-off (Source: Microchip
Technology)
DESIGN
false turn-on of the device. This can result in a
short-circuit and a shoot-through current.
▶ Switching losses: The parasitic inductance
slows down the switching speed and increases
the switching time. This prolongs the transition
period when both the voltage and the current
are high, which leads to higher switching losses.
inductances in the power system loops to avoid these
Therefore, it is essential to reduce the parasitic
problems and improve the efficiency and reliability of
the power system.
HARNESSING SiC CAPABILITIES WITH
MICROCHIP’S SP6LI PACKAGE
SiC devices offer many advantages over conventional
silicon devices, such as higher breakdown voltage,
lower on-resistance, faster switching speed and higher
operating temperature. However, to fully exploit the
potential of SiC devices, it is necessary to have a
suitable package that can handle the high-current,
high-frequency and high-efficiency requirements of the
power system.
Microchip’s SP6LI package is a novel solution that
is designed to reduce parasitic inductances and
unleash the performance of SiC devices. The SP6LI
package is a phase-leg module that consists of two
SiC MOSFETs and two SiC Schottky diodes in a half-
bridge configuration. The SP6LI package has a very low
stray inductance of 2.9 nH, which is achieved by using
a symmetrical layout, a direct-bond–copper substrate
and a low loop area.
The SP6LI package offers several benefits for the
power system, such as:
FEBRUARY 2024 | www.powerelectronicsnews.com 27