Page 57 - EE Times Europe Magazine – November 2023

EE|Times EUROPE 57

Soitec’s SmartSiC to Hit the Road in 2024

At Bernin 4, Soitec has opted for ramp-up
flexibility between 150 and 200 mm. “The
adoption of SmartSiC is in both 150 mm and
200 mm, and we didn’t want to choose one
size or another, as we think both markets will
grow,” Barnabé said. “The 150-mm [wafer
size] has already taken off, while the 200-mm
[wafer adoption] is in the making. We have
chosen to create a flexible, size-agnostic fab,
to be able to grow in both 150 mm and 200
mm, depending on needs.”
By 2028, Soitec intends to produce more
than 5 million wafers a year, across all pro-
duction sites and wafer sizes.

FROM SMARTSiC TO SMARTGaN AND
MORE
In the medium to long term, Soitec has identi-
fied two main drivers of profitability. The first
European Commissioner Thierry Breton (fifth from left) and French minister delegate of is the growth trajectory of the semiconductor
industry Roland Lescure (third from right) were on hand for Soitec’s Bernin 4 ribbon- market; the second is the adoption trend
cutting ceremony. (Source: Anne-Françoise Pelé/EE Times Europe) beyond its core silicon-on-insulator products
to piezo-on-insulator, SiC and GaN products.
The advantage of a polySiC wafer is that it just getting started. It’s not the end of the “We have products around GaN that will
is extremely conductive, conducting electric story. We’re continuing to carry out advanced increasingly penetrate the market, with the
current 8× better than a monoSiC wafer, R&D and to think about uses and optimiza- SmartGaN solution in particular, which will
Sabonnadière said. “This represents an energy tions for SmartSiC, including increasing the mirror what we are doing with SmartSiC but
savings of between 15% and 20% compared reusability.” for GaN, with new applications to address
with conventional SiC in MOSFETs and market needs,” Barnabé said.
diodes.” ‘SIZE AGNOSTIC’ FAB A SmartGaN product will be developed
Soitec further claims its SmartSiC tech- After demonstrating the quality and perfor- over the next few years, Barnabé said. “For
nology enables the production of 10× mance of 150-mm SiC engineered substrates SmartSiC, the pilot unit with Leti enabled us
more high-quality SiC substrates from one for high-voltage power devices, Soitec moved to significantly reduce the lead time needed
monocrystalline SiC substrate. to the next step, releasing in May 2022 what it to understand how the market worked. We
The prime-quality SiC donor wafer can be said was the world’s first bonding of a will benefit from these gains with SmartGaN,
reused multiple times, Sabonnadière said. 200-mm monocrystalline SiC donor wafer which will consist of a thin layer of high-
“Since we reuse 10× the value of a monoSiC onto a 200-mm polycrystalline SiC han- quality GaN that we will bond to a silicon or
[donor] wafer, if it’s of very good quality, you dle wafer. In December, it announced an non-silicon handle wafer so as to address the
will have 10 wafers of very good quality.” This agreement with STMicroelectronics to qualify power electronics market above 1,200 V and
reusability effect improves manufacturing and certify Soitec’s SmartSiC technology to very high radio frequencies.”
yields and allows more devices on a single produce 200-mm SiC substrates. To explain the acceleration phase of
wafer. The 18-month qualification and certifi- SmartGaN, which is expected to be faster than
“From 50,000 wafers entering the fab, we’ll cation phase is progressing “as per plan,” that of SmartSiC, Menon pointed out that
produce 500,000 wafers, and on each Sabonnadière told EE Times Europe. He Soitec’s industrial infrastructure includes a
[200-mm] wafer, the chipmaker will be able declined to identify other customers but said GaN epitaxy center in Belgium. This was not
to add 25% more components,” Sabonnadière that more than 1,000 prototypes had been the case for SiC. “We didn’t have a source
said. sent to customers and prospects to date. of monoSiC,” he said. “Here, it’s the syn-
Soitec claims the monoSiC donor wafer can “We had 20 prospects in July and [have] ergy between GaN epitaxy technology and
be reused 10 times. Why not more? “Because nearly 30 prospects today, with accelerating SmartCut technology, which is well-known
we guarantee 10,” Sabonnadière told EE [dynamics] in the four car-making regions of in the company and which we know how to
Times Europe. “We say 10, [and] technically the world,” he said. “We are no longer at the industrialize. All these factors will help speed
we [can] do 15, but there is nothing to stop prototype stage. This is industrialization. And things up.”
us going further. It is part of the advanced reasonably, by the end of 2024, we will be see- Asked whether a SmartGaN factory was
research we are pursuing with Leti, among ing the first EVs featuring power components planned, Barnabé replied, “We will see.”
others, to [extend] our value proposition.” with SmartSiC inside.” SiC and GaN have bright futures, but
When EE Times Europe asked whether the The Bernin 4 fab will have 2,500 square diamond could well prove to be the ultimate
quality of the SiC donor wafer could dete- meters of cleanroom space, but only wide-bandgap semiconductor material for
riorate with reuse, his answer was no. “The 1,500 square meters are currently equipped. applications in high-power electronics. Soitec
quality doesn’t change. It’s more a question The first wafers are coming off the line in says it has already sketched out a medium- to
of the mechanical grip, like a plate that you November, with production rising to several long-term roadmap. “This is very advanced
handle and which gradually gets scratched. thousand wafers by next year and research,” Sabonnadière told EE Times
[But] the intrinsic quality of the wafer does 500,000 wafers per year at full capacity by Europe. “SmartGaN is the next move, and the
not change.” 2028. The 200-mm wafers are scheduled to move after that is diamond.”
Sabonnadière added that “SmartSiC is enter production in March. SmartDiam, maybe. ■

www.eetimes.eu | NOVEMBER 2023