Page 29 - EE Times Europe Magazine – June 2024

EE|Times EUROPE 29

Certifying RISC-V: Industry Moves to Achieve RISC-V Core Quality

type and combinations are important. Check- However, a common organization can propel
ing branch prediction, verifying instruction such an initiative, and RISC-V International is
privilege levels and ensuring exceptions are doing just that.
handled correctly are just a few examples.
Another aspect of instruction testing is RISC-V CERTIFICATION For reader inquiries and address changes,
please contact: christiane.lockner@aspencore.com
to ensure compliance with the official ISA RISC-V International and other organizations To unsubscribe, please go to:
specification. Various tests are available, but have already implemented a RISC-V ISA com- www.eetimes.eu/unsubscribe/
they achieve only some of this architectural pliance test suite. While the suite is a useful
test requirement. start, it is in no way comprehensive enough to
Instruction-level, architectural testing is be solely replied upon. RISC-V Aspencore Media GmbH
just the start. Up to 80% of processor execu- International’s board recognized the need to Frankfurter Straße 211
tion consists of load-store operations, and set up a rigorous certification program that 63263 Neu-Isenburg
Germany
these must be efficient. The same applies to would provide processor suppliers with an
the interrupt mechanisms and many other independent assessment of the performance EE TIMES EDITORIAL MANAGEMENT
Cyrus Krohn, Editor-in-Chief, EE Times,
interfacing requirements. Functional opera- of their devices, yielding information on cyrus.krohn@aspencore.com
tion and performance-related issues must be which their customers could rely. Anne-Françoise Pelé, Editor-in-Chief, EE Times Europe,
checked together, as read-write hazards can Certification programs exist for other afpele@aspencore.com
Echo Zhao, Chief Analyst, echo.zhao@aspencore.com
cause unexpected problems that prove diffi- industry standards, such as Wi-Fi, USB and Yorbe Zhang, Head of AspenCore APAC,
cult to debug. Such a concerted effort requires PCIe. While these interface protocols require yorbe.zhang@aspencore.com
in-depth, microarchitectural testing, which extensive test suites, their verification is sim- GLOBAL ASPENCORE EDITORS
in turn requires test synthesis that combines pler than verifying a full processor core. Arm Matthew Burgess, matthew.burgess@aspencore.com
Anthea Chuang, anthea.chuang@aspencore.com
different test sets to weed out complex, and Intel undoubtedly have internal sign-off Nitin Dahad, nitin.dahad@aspencore.com
unpredictable corner cases. processes for their new cores, but these are Maurizio Di Paolo Emilio,
proprietary. As such, no public program of maurizio.dipaolo@aspencore.com
Yvonne Geng, yvonne.geng@aspencore.com
RISC-V International’s this nature to certify a device as complex as a Amy Guan, amy.guan@aspencore.com
Susan Hong, susan.hong@aspencore.com
processor core that can be applied to a range
board recognized the need of core architectures has been created before, Illumi Huang, illumi.huang@aspencore.com
Barbara Jorgensen, barb.jorgensen@aspencore.com
Majeed Ahmad Kamran, majeed.kamran@aspencore.com
for a certification program to and it is a daunting challenge. Clover Lee, clover.lee@aspencore.com
The RISC-V board recently formed the
Shao Lefeng, lefeng.shao@aspencore.com
provide processor suppliers RISC-V Certification Steering Committee Jenny Liao, jenny.liao@aspencore.com
Elaine Lin, elaine.lin@aspencore.com
(CSC) to tackle the task. Members include
with an independent commercial RISC-V users, processor provid- Luffy Liu, luffy.liu@aspencore.com
Stefani Muñoz, stefani.munoz@aspencore.com
Challey Peng, challey.peng@aspencore.com
assessment of the ers, test suite providers and other experts in Gina Roos, gina.roos@aspencore.com
this area. The committee is new but is moving
Fendy Wang, fendy.wang@aspencore.com
performance of their devices. aggressively to come up with a concrete plan Sally Ward-Foxton, sally.wardfoxton@aspencore.com
Demi Xia, demi.xia@aspencore.com
that addresses what tests might be used, how Franklin Zhao, franklin.zhao@aspencore.com
the program would operate, to what degree Momo Zhong, momo.zhong@aspencore.com
The core should also be tested in a the tests would check overall architecture and CONTRIBUTING EDITORS
system-on-chip. Depending on the core—or other definitional questions. By the end of the Pat Brans, pdbrans@gmail.com
multicore—complexity, we start to see coher- year, the CSC should have a comprehensive Robert Huntley, robert@seventyfourhundred.com
Saumitra Jagdale, saumitra@opencloudware.com
ency issues, security vulnerabilities, complex plan and will be well on its way to implement- Egil Juliussen, egil@norskeagle.com
interrupts and many more. ing it. Stefano Lovati, slovati@gmail.com
This is extreme verification, and it is what The RISC-V board fully expects the CSC Rebecca Pool, editorial@rebeccapool.com
Anton Shilov, ashilov@gmail.com
drives processor companies like Arm to invest to remove a critical potential barrier to the Ann Thryft, athryft@earthlink.net
so much. It is unreasonable to expect a small full deployment of RISC-V processors by PRODUCTION
team to build such a verification environment. providing a quality stamp of approval for the Adeline Cannone, Design Director,
The only way to achieve an appropriate level most complex devices that will be accepted adeline@cannone.com
of verification by smaller teams is dramatic across the semiconductor industry. This is no Lori O’Toole, Chief Copy Editor, lotoole@aspencore.com
Diana Scheben, Senior Copy Editor,
test content reuse. mean feat, and it will require a broad range diana.scheben@aspencore.com
One advantage of a common ISA is that of expertise to achieve verification levels not SALES & MARKETING
it enables multiple teams to combine forces previously seen in the public domain. But it Christiane Lockner, christiane.lockner@aspencore.com
by combining test suites. A vehicle for such is absolutely necessary to achieve the same The Hufmann Agency, victoria@hufmann.info,
norbert@hufmann.info
a common reusable test set is a system-level quality expectation for RISC-V cores as we Todd Bria, todd.bria@aspencore.com
verification intellectual property component observe for its commercial counterparts. Cyrus Krohn, Vice President, Publisher — AspenCore
(SystemVIP) targeting RISC-V. With this RISC-V is about to get a whole lot more
approach, a commercial or other organization reliable. ■ Copyright© All rights reserved. No part of this publication
may be reproduced or transmitted in any form or by any
would build a common test set by leveraging means without the prior express written permission of
economies of scale, spreading the investment REFERENCE AspenCore Media. Although we make every effort to present
up-to-date, accurate information, EE Times Europe will not
across many core developments. This is the 1 BCC Research (December 2022). “RISC-V be responsible for any errors or omissions or for any results
obtained from the use of such information. The magazine
purpose of commercial verification com- Technology: Global Market Outlook.” will not be li able for any loss caused by the reliance on
panies, as well as open-source projects by tinyurl.com/4te8z2y3 information obtained on this site. Furthermore, EE Times
Europe does not warrant the accuracy or completeness
corporations that include Google. of the information, text, graphics in this magazine. The
Of course. such cooperation is difficult Dave Kelf is CEO of Breker Verification opinions expressed in the articles are those of the authors
and not necessarily the opinions of the publisher.
between commercial, competitive entities. Systems.
www.eetimes.eu | JUNE 2024