Page 28 - EE Times Europe Magazine – June 2024

28 EE|Times EUROPE

OPINION | AUTONOMOUS VEHICLES | SECURITY

Certifying RISC-V: Arguably, one of the most important

Industry Moves to RISC-V market characteristics thus far is that
most of those 13 billion processors have been
relatively small, embedded devices. But we
Achieve RISC-V Core are now seeing the advent of larger, multicore
application processors in complex systems,
with an inevitable impact on verification
Quality solutions, given the processors’ far greater
complexity.
In response, RISC-V International’s board
has launched a certification committee to
By Dave Kelf, Breker Verification Systems address the need for a provable quality bench-
mark for RISC-V.

At the RISC-V Summit North America in November 2023, Simon VERIFYING A PROCESSOR
Davidmann, CEO of Imperas (now Synopsys), delivered a surprising Processor verification is a complex business
keynote. His message: While RISC-V was an enormous leap forward, with too many facets to cover in this short
the limited focus on quality could ultimately kill the initiative. This article. However, even in the case of a simple,
was a view shared by many stakeholders. single-core embedded device, a large series
Davidmann went on to explain that a quality expectation had of instructions in an almost-infinite range
been set across the semiconductor industry by companies like Arm of combinations can be applied to make the
and Intel. Bugs in their processors have been extremely rare, and device react in many different ways.
users rely on that quality level, as a processor bug could kill an end Intelligent, random instruction generators
product. Davidmann noted that Arm spends more than US$150 million on verification annually, are often deployed for a more superficial
runs a staggering 10 (greater than the number of miles in a light year) verification clock cycles check of the architecture. Checking that the
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per core and has 30 years of experience under its belt. This is made easier by retaining complete processor does the right thing, based on the
control of the instruction set. instruction stream applied, requires the use of
RISC-V users expect this “Arm quality” level, because without it, their designs will fail. But either self-checking tests or a golden model
how can RISC-V core providers hope to meet this quality goal, and how can they prove it? of a RISC-V processor for comparison, both
of which are hard to produce. The instruction
RISC-V: NEW PROCESSOR THINKING
Before the advent of RISC-V, most processor
instruction set architectures (ISAs)—the
fundamental code specifications used to drive
the device—were the protected intellectual
property of the company that developed the
processor. This protection was critical to the
company, as it allowed ecosystem control
and blocked competition, enabling favorable
business models.
Along came the RISC-V open ISA. Any
company could use the instruction set for
its processor implementation, software
stack, tools and other ecosystem elements.
Business models would no longer be dictated
by the ISA copyright. In addition, the RISC-V
ISA was more flexible than others, allow-
ing the inclusion of differentiating custom
instructions.
The semiconductor industry was enthusi-
astic. Coincident, unpopular business model
changes from Arm drove companies to
start RISC-V initiatives, and RISC-V gained
considerable momentum. BCC Research
estimated the market for RISC-V technology
in 2021 at US$500 million, with an expected
growth rate of 33%, to US$2.7 billion by
2027. Today, RISC-V International, the ISA
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governing body, reports 3,950 members in
70 countries, with 13 billion RISC-V IP cores A typical RISC-V verification stack is a complex undertaking that needs a comprehensive
on the market. test plan. (Source: Breker Verification Systems)

JUNE 2024 | www.eetimes.eu