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        EDITOR’S LETTER


        Scale FD-SOI to 7 nm? Yes, We Can






                            During the consultative phase leading   logical sovereignty does not entail isolationism, protectionism or
                            up to the Chips Act, the EU asked its three   the end of liberal trade. It is about fostering more bilateral collabo-
                            champions of microelectronics research—  rations with like-minded countries and strategic partners. It is also
                            CEA-Leti, imec and Fraunhofer—how they   about implementing an industrial policy, creating adequate indus-
                            might support the European challenge of   trial capabilities, such as megafabs, and investing at every level of
                            doubling production by 2030, seeking their   the value chain.
                            recommendations for a strategic road-  “Our vocation is not to do everything here [in Europe] but to main-
                            map. Their proposal included establishing   tain our strategic autonomy,” Breton said. “Projects will emerge. Today,
                            a fully depleted silicon-on-insulator   we have 65 projects in Europe, worth over €100 billion, in pipelines.”
        (FD-SOI) pilot line in Grenoble, France, to help scale FD-SOI process   As part of the Chips Act, the EU will invest €11 billion over the next
        technology to 10 nm.                                  seven years through the Chips for Europe Initiative and develop at
          Why set the target at 10 nm when you can aim further? European   least three pilot lines to industrialize the production process of the
        Commissioner Thierry Breton raised the ante, proposing to scale   most advanced node sizes: one at imec for sub-2-nm gate-all-around
        FD-SOI down to 7 nm. Criticism was rife, but he persisted.  (GAA) process technology development, one at CEA-Leti for FD-SOI
          “If we set ourselves the ambition to get there, and to get there   process technology at 10 nm and below, and one at the Fraunhofer
        together at the European level, we will get there,” Breton said in   Institute for heterogeneous system integration.
        September at the inauguration ceremony for Soitec’s SiC wafer fab in   To take advantage of the Chips Act and innovate in the global semi-
        Bernin, near Grenoble.                                conductor industry, many believe that the EU must strive to become a
          “As part of the Chips Act, we have set aside funds to finance three   champion of advanced chip design, not necessarily chip manufacturing.
        pilot lines, including a billion-dollar FD-SOI pilot line, where we’ll   Breton is not among them.
        be able to carry out all possible tests,” he told the assembly. “We are   “Let me be clear: There can be no industrial policy without a fab,”
        going to help you go below 10 nm, or even 7 nm, because you abso-  he said. “The myth of a company without a fab has never worked, and
        lutely have to be ready for the markets of the future.”   certainly not in the modern world. We are supporting this reindustrial-
          Improving the energy efficiency of power semiconductors is seen   ization while continuing to work with our partners.”
        as essential for realizing carbon neutrality. CEA-Leti claims FD-SOI is   Opinions may diverge on the specifics, but they always converge on
        25% faster than equivalent transistors on solid silicon and consumes   defending the EU’s common good. “Europe must take its destiny back
        up to 40% less energy.                                into its own hands,” Breton concluded. ■
          FD-SOI has its roots in the Grenoble area and has been a key R&D
        focus for more than 20 years at CEA-Leti. The technology uses an
        ultra-thin insulator layer on the silicon substrate and a very thin
        silicon film to better control transistor behavior. The architecture
        also enables the switching speed to be dynamically modulated during
        operation, providing an effective means of optimizing power con-
        sumption when speed is less critical. Because of its planar structure,
        FD-SOI is less complex to manufacture than FinFETs.
          Gone are the days when Europe invested only in research, sending                     —Anne-Françoise Pelé,
        production offshore, Breton said. The Chips Act will either directly             editor-in-chief of EE Times Europe
        finance or authorize the financing of a competitive European indus-
        trial base across the semiconductor value chain.
          But protecting the EU’s
        internal market and industrial
        value chains will require more
        than funding. “We will be able
        to provide financial support, but
        we need breakthrough technolo-
        gies,” Breton said. “We are going
        to help you take risks, because
        the market is there, and we can’t
      IMAGE: ANNE-FRANÇOISE PELÉ  and the U.S.”
        just leave it to the Taiwanese
          We must never be naive. Any
        alliance of politics and industry
        boils down to power struggles
        and arbitrations to defend each
        faction’s interests and keep the
        value chains moving.
          The EU’s quest for techno-

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