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Server Processors in the AI Era: Can They Go Greener?

a special processor architecture that is
specifically designed to maximize the ratio
of performance to power consumption.
Full-custom ASIC processors are already
deployed for video and recommender systems
as well as AI training and inference; this trend
will increase and allow for squeezing more
performance/power juice. In this context,
application-specific instruction set processors
(ASIPs), in which the instruction set archi-
tecture is optimally tailored for a specific
application, are a viable solution for addi-
tional environmental gains.
Packaging technologies like chiplets, in
which a big processor is split into smaller dice
to gain lower cost and better yield, allow for
improved power management and are already
being employed. Chiplets make it possible to
increase the effective die area considerably
beyond the reticle size, and thousands of
Figure 2: Power savings accumulation through the data center units resulting from a 1-W small cores have been demonstrated that, in
power savings at the processor. From left to right, the bars plot the accumulated power combination with intelligent energy manage-
consumption savings across the data center. (Source: Vertiv, 2023 ) ment, make it possible to achieve an optimal
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performance-to-power ratio.
While all of these directions fall within
Therefore, the server processor power the metric shown in the following equation: the realm of processor design, new algo-
consumption is significant. According to a rithms for redefining AI models so that they
report from infrastructure provider Vertiv, Performance ÷ (Cost × Area × Power) require less computing power and memory
1 W of power saved at the server processor where performance is the number of bandwidth should also be considered, as has
translates into a total savings of 2.84 W floating-point or integer operations per happened in convolutional neural networks
across the data center. Figure 2 illustrates second and where die cost, area (mm , (i.e., compression). ■
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how a 1-W power savings at the processor reticle-size limited) and power (W) are
affects different components of the data self-explanatory. From an environmental per- REFERENCES
center and leads to about a 3× power savings spective, the primary objective is to maximize 1 Rozite et al. (July 11, 2023). “Data Centres and
in total. For example, 1 W saved at the pro- the performance-to-power ratio. Improv- Data Transmission Networks.” International Energy
cessor leads to a 0.18-W savings in DC/DC ing performance in parallel to reducing Agency. tinyurl.com/24bj24ad
power conversion, 0.31 W in AC/DC power power consumption is usually a conflicting 2 Roser, M. (Dec. 6, 2022). “The brief history of
conversion and so forth. Notably, requirement. There is a vicious circle that artificial intelligence: The world has changed fast –
1.07 W of cooling power is saved for every works against maximizing this equation, as what might be next?” Our World in Data.
watt of processor power saved. its variables are interrelated via their mutual tinyurl.com/nhz8hws6
dependence on the transistor density (tech- 3 Bastian, M. (March 25, 2023). “GPT-4 has more than
Despite great efforts nology node), transistor count, memory size, a trillion parameters.” The Decoder.
clock frequency, driving voltage, number of
tinyurl.com/ruaprxjk
to improve processors’ cores and threads, wafer yield and more. 4 Hines, K. (July 19, 2023). “OpenAI Increases GPT-4
We are already practicing power manage-
efficiency, the rapid growth ment techniques, such as voltage-frequency Message Cap To 50 For ChatGPT Plus Users.” Search
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of AI workloads has resulted scaling and clock gating. Logic synthesis and 5 energy efficiency with 3D die-stacking graphics
Zhao et al. (Dec. 1, 2013). “Optimizing GPU
physical design optimization can also come to
in a substantial increase in the rescue. So what’s next? memory and reconfigurable memory interface.”
Gate-all-around technology will increase
energy consumption over the the driving current per area in tandem with ACM Transactions on Architecture and Code
Optimization, 10(4), pp. 1–25.
past decade. better channel control that reduces static tinyurl.com/ym9j6nj3
(leakage) power. Dropping the nominal core 6 Vertiv. (2023). “Energy Logic: Calculating and
voltage (V DD ) to 0.65 V would further save on Prioritizing Your Data Center IT Efficiency Actions.”
The current average rack density is about dynamic power (compared with FinFET-based tinyurl.com/4wfpa949
10 kW per rack. Therefore, a savings of even a processors). Novel advanced logic approaches 7 CoreSite. (2023). “Facing the Data Center Power
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few percentage points at the server proces- are emerging, such as Quasi-CMOS, in which Density Challenge.” tinyurl.com/yeyunvn7
sor can translate into a significant power a modified circuit topology enables a signifi- 8 NeoLogic. “Powering the Next Generation
savings at the rack level and positively affect cant improvement in the Processors: A New VLSI Design Paradigm.”
both electricity usage and greenhouse gas performance-to-power ratio. 8 neologicvlsi.com
emissions. Furthermore, the best possible
While the advancement of processors’ performance-to-power ratio for a specific Avi Messica is co-founder and CEO, and
performance is power-limited, other factors application may not be attainable via a Ziv Leshem is co-founder and CTO, both of
can’t be ignored. Usually, we seek to maximize general-purpose processor but rather via NeoLogic.

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