Page 8 - PEN eBook February 2024

COVER STORY – DESIGN
temperature and time to provide the optimum
‘stress’ while avoiding inducing failures,” he added. solution that can be customized to accommodate
Moreover, wafer-level burn-in optimizes production
yield by reducing the number of defective devices
that proceed through further manufacturing
steps, such as assembly into multi-chip modules,
heterogeneous integrations and package parts.
PRECISION AND SCALABILITY
Wafer electrical testing attains a superior level of
accuracy and expandability by employing numerous
precise, calibrated electrical sources and measuring
tools for each wafer.
“At Aehr, we ensure the precision of the instruments
integrated into our systems using calibration
procedures that verify and adjust performance
to known industry standards and adhering to
traceability requirements of such standards,”
Rogers said.
Figure 2: Aehr’s FOX-XP with Integrated WaferPak Aligner
(Source: Aehr Test Systems)
Aehr’s FOX test system platform is architected for
massively parallel testing using a modular system
design and software that implements real-time
monitoring and controls. The company developed
data analysis and reporting tools that identify trends
or anomalies automatically, informing the end user
of any potential issue. The FOX-XP with Integrated
WaferPak Aligner, for instance, achieves advanced
precision in wafer handling and probe alignment
using optical alignment with multiple cameras to
ensure accurate wafer-to-probe alignment and
placement in a WaferPak contactor (Figure 2).
8 FEBRUARY 2024 | www.powerelectronicsnews.com
SEMICONDUCTORS
The FOX-XP solution is a versatile test/burn-in
DiePak Carriers for individual die/module testing.
A DiePak Loader, which is optional, can be used
to automate the process of loading and unloading
devices into FOX DiePak Carriers. This module test
system supports both full wafer and singulated die
burn-in and test.
MODULAR ARCHITECTURE
The design of Aehr’s testing systems has followed a
modular approach. The FOX-NP system, for instance,
utilizes identical test hardware as the FOX-XP.
As Rogers explained, Aehr’s “modular architecture”
used on both the FOX-NP (one- or two-wafer
capacity) and the FOX-XP (up to 18-wafer capacity)
ensures consistent test capabilities and an intact
transition from a small-lot engineering and NPI
setup to a fully automated, high-volume production Cascode GaN Power
platform.
A perfect correlation between the results obtained Devices in Cu-Clip
from the FOX-NP and FOX-XP systems is ensured by
this modular design.
“The modular architecture used in either the Package for Superior
FOX-NP or FOX-XP systems is assembled and tested
independently of the final system configuration, Power-Conversion
to the same performance and reliability standards
regardless of which platform they are integrated
[into],” Rogers said. Moreover, the software for both Performance
the FOX-NP and FOX-XP is identical, providing a
seamless user experience.
By Sonu Daryanani, contributing writer for Power Electronics News
This correlation is extremely critical, especially in
ensuring a painless transition from the
engineering-oriented FOX-NP, in which product The cascode architecture with power gallium nitride use of a high-threshold–voltage (V ) MOSFET, the
th
qualification was completed, to the massively parallel devices uses a depletion-mode (d-mode) HEMT gate drive becomes very robust, allowing for a high
FOX-XP production systems, in which correlation and device and offers many advantages in higher-power– overdrive margin and external gate voltages (V ) of
gs
maximum yield are required. The synergy between conversion applications. Improved packaging can help ±20 V. This is in sharp contrast to the low V (<2 V)
th
the FOX-NP and FOX-XP platforms affords the utilize the benefits of GaN to its fullest extent. This typical in enhancement-mode (e-mode) GaN devices,
manufacturer a wide range of test capabilities for article details Nexperia’s development of the copper where maximum V is typically limited to 6–7 V, which
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various products, such as silicon photonics and GaN (Cu)-clip CCPAK package for its cascode power GaN restricts overdrive. The low V also places greater
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and SiC semiconductors. devices, as presented at the December 2023 PowerUP constraints in the gate drive, the gate coupling from
Virtual Expo. drain-switching transitions and added parasitic
inductances from the package and board layout to
ADVANTAGES OF CASCODE GaN minimize noise and oscillation that could cause a
ARCHITECTURE parasitic turn-on.
In the cascode architecture, a normally on d-mode
HEMT is coupled with a normally off low-voltage silicon The use of the d-mode GaN HEMT improves its
MOSFET device, as shown in Figure 1. on-state performance with improved carrier mobility,
as well as the off state with a much lower gate
The silicon device controls the gate drive, hence leakage from the cascode silicon device. The improved
offering flexibility in the use of common gate drivers on-state performance translates to higher-current–
that are used to drive silicon MOSFETs. With the rated devices. Another key advantage of the cascode
FEBRUARY 2024 | www.powerelectronicsnews.com 9