Page 6 - PEN eBook February 2024

COVER STORY – DESIGN
Wafer-Level Test and
Burn-In Advances GaN
Reliability
By Maurizio Di Paolo Emilio, editor-in-chief of Power Electronics News
Aehr Test Systems disclosed that an initial
customer order for a FOX WaferPak Aligner and
a FOX-NP wafer-level test and burn-in system
intended for gallium nitride power devices has been
received. The customer, a prominent international
provider of semiconductor devices utilized in power
infrastructure and electric vehicles, further expands
the roster of significant clients that utilize Aehr’s FOX
products to conduct wafer-level test and burn-in of
wide-bandgap (WBG) compound semiconductors.
It is anticipated that the FOX-NP system, which
comprises the FOX WaferPak Aligner, will be delivered
and set up during the ongoing fiscal quarter.
Part of the reason the company chose to order a
system from Aehr was because of Aehr’s ability to
offer a complete solution that lets thousands of
devices be put under temperature and electrical
6 FEBRUARY 2024 | www.powerelectronicsnews.com
stress while they are still on wafers. Aehr’s
cutting-edge technology provides important
geolocation data across the wafer without affecting
the long-term stability or lifespan of good devices.
It does this by causing early-life failures that would
otherwise happen in the field.
Aehr Test
Systems’
Vernon Rogers
AEHR TEST SYSTEMS
Wafer-level test and burn-in is a crucial procedure
in the semiconductor industry to guarantee the
dependability and excellence of semiconductor
COVER STORY – DESIGN
devices. The significance of these tests lies in their dynamic negative and positive voltages. The company
capacity to detect and rectify potential flaws and has created exclusive and patented techniques to
malfunctions in semiconductor devices before ensure that all the thousands of dies on GaN and SiC
their packaging and delivery to customers. By doing wafers remain in complete contact while preventing
these tests at the wafer stage, manufacturers can arcing in high-voltage situations, especially in
identify and resolve problems at an early stage of fine-pitch geometries.
manufacturing, hence minimizing the likelihood of
defective devices being released to the market.
At the forefront of this technology is Aehr Test
Systems, a global supplier of test equipment used
for the process of burning in and testing integrated
circuits that are used in logic, optoelectronic and
memory applications. Headquartered in Fremont,
California, the company offers a wide portfolio
of products used for testing and burning in
semiconductor devices at various stages, including
wafer level, singulated die and package part form.
In an interview with Power Electronics News,
Vernon Rogers, EVP of sales and marketing at Aehr
Test Systems, provided insights on these innovative
testing methodologies, explaining how they can
assess the quality and reliability of semiconductors,
including emerging WBG materials like GaN and
silicon carbide.
WBG TESTING SOLUTIONS
and frontrunner in the burn-in and semiconductor
Aehr Test Systems is acknowledged as a trailblazer
test sector, possessing a patent portfolio that
encompasses groundbreaking ideas in fields like
portable WaferPaks and exceptionally parallel testing
capabilities. Recently, the company received an initial
customer order for a FOX-NP wafer-level test and Figure 1: Aehr’s FOX-NP system (Source: Aehr Test Systems)
burn-in system (Figure 1) and a FOX WaferPak Aligner
intended for GaN power devices.
Wafer-level burn-in is a crucial step in WBG
“Our FOX systems employ an innovative combination semiconductor manufacturing. It involves subjecting
of thermal control mechanisms and electrical stress the wafers to elevated temperatures and electrical
conditions to perform wafer-level burn-in testing on stresses for a specified period, as defined by the
gallium nitride, along with silicon carbide and other customer’s high-temperature gate bias,
devices,” Rogers said. high-temperature reverse bias, time-dependent
dielectric breakdown, threshold voltage and other
Aehr’s unique compact system architecture test specifications.
supports full wafer test and thermal control and
wafer handling in a form factor called a “Blade,” “Subjecting each wafer to accelerated stress
in either a 3.4-inch (8.5-cm) height test for higher conditions, such as elevated temperatures and
parallelism or a 6.8-inch (17.2-cm) height test increased voltage levels, help uncover latent defects
for more channels. The FOX platform features a or weaknesses in the devices that might lead to
sophisticated thermal control system that offers early-life failures,” Rogers said.
precise cold and hot thermal control to each
wafer. This is achieved by applying electrical stress “The challenge with test and burn-in is to not
conditions to each wafer using Aehr’s exclusive exceed the device limitations that can actually
precision power supplies and measurement create latent defects, or ‘walking wounded,’ devices,
instruments, which can generate a wide range of and this requires a careful balancing of electrical,
FEBRUARY 2024 | www.powerelectronicsnews.com 7